The present invention relates generally to internal wiring of a semiconductor memory apparatus and more particularly to a semiconductor memory apparatus having a memory cell array divided into a plurality of n-blocks where n is not a power of 2.
A DRAM (dynamic random access memory) is an example of a conventional semiconductor memory device. A DRAM has an array of memory cells. Each memory cell stores one bit of data. A DRAM cell is made up of a cell transistor and a cell capacitor. The cell capacitor stores data and the cell transistor provides an access path to the data on the cell capacitor. The cell capacitor stores data by either the presence or absence of charge on the capacitor in accordance with the stored data value.
The memory cells are arranged in a matrix of rows and columns. A word line is electrically connected to a plurality of cells in the row direction and bit lines are electrically connected to a plurality of memory cells in the column direction. A memory cell is formed at the intersection of a bit line and a word line. The cell transistor is electrically connected to a word line at a control gate. The cell transistor provides a controllable impedance path between a bit line and the cell capacitor.
When reading data from a memory cell, a word line is selected and the cell transistor provides a low impedance path from the bit line to the cell capacitor. This allows electrical charge to be transferred between the cell capacitor and the bit line. The charge sharing between the cell capacitor an the bit line provides a data signal to be placed on the bit line. The data signal is a change in the bit line potential based on the addition or removal of charge on the bit line. The magnitude of the data signal is determined by the ratio of the capacitance value of the bit line (Cd) and the capacitance value of the cell capacitor (Cs). The smaller the capacitance ratio (Cd/Cs), the larger the magnitude of the data signal placed on the bit line. This can increase the noise margin when reading data. The greater the capacitance ratio (Cd/Cs), the smaller the magnitude of the data signal placed on the bit line. This can decrease the noise margins when reading data. For these reasons, it is desirable to reduce the capacitance of the bit line so that the capacitance ratio (Cd/Cs) does not become too large.
In a conventional semiconductor memory device, the memory cell array is divided into a plurality of blocks. This reduces the number of memory cells connected to one bit line, thus decreasing the bit line capacitance and improving the data signal on a bit line during a read operation. When the number of blocks increases, the chip size typically increases. This can be due to the increased number of sense amplifiers required and circuitry associated with selecting a block. Thus, the number of blocks is typically determined by a maximum allowable capacitance ratio (Cd/Cs). For example, in a 256 Mbit DRAM, the memory cell array may be divided into sixteen blocks and there may be 512 memory cells connected to one bit line. This can give a capacitance ratio of approximately 7 to 8.
The block division of the memory cell array in a conventional semiconductor memory device will now be explained.
Referring now to FIG. 1, a 256 M-bit (megabit) synchronous DRAM (SDRAM) is set forth in a block schematic diagram and given the general reference character 100.
SDRAM 100 includes four banks (100A to 100D). Each bank has a memory density of sixty-four M-bits divided into four sub-arrays SARY. Each bank can provide 16 bits of data onto the external data pins (DQ0 to DQ15). The 16 bits of data are divided into four groups. DQ0 to DQ3 form one group of data. DQ4 to DQ7, DQ8 to DQ11, and DQ12 to DQ15, respectively, form the other groups. Each sub-array SARY can store bits from one group of data.
Referring now to FIG. 19, the bit-map illustrating the address mapping of a conventional sub-array is set forth.
The sub-array is divided into sixteen blocks (XBLK0 to XBLK15) with block XBLK0 illustrated by right cross-hatching. Each block has five-hundred-and-twelve rows of memory cells. Each block (XBLK0 to XBLK15) is further divided into four small equal block sections, which can be addressed by column addresses. A block section from block XBLK15 is illustrated by left cross-hatching. Each sub-array has a total of sixty-four block sections of memory cells. In the example illustrated in FIG. 19, the sixteen blocks (XBLK0 to XBLK15) are selected by row addresses X9 to X12 as illustrated in the bit map. The four block sections in one sub-array are selected by column addresses Y7 and Y8. In this way, one of the sixty-four block sections is selected according to the value of row addresses X9 to X12 and column addresses Y7 and Y8. For example, the left cross-hatched block section is selected when row addresses X12 to X9 have the value (1111) and column addresses Y8, Y7 have the value (11).
Sense amplifiers are provided for each block (XBLK0 to XBLK15). Each bit line (or bit line pair) within a block (XBLK0 to XBLK15) can be electrically connected to a sense amplifier. The bit lines are disposed in the vertical direction in the sub-array illustrated in FIG. 19. Each bit line within a block (XBLK0 to XBLK15) is connected to five-hundred-and-twelve memory cells. Each block has one-hundred-and-twenty-eight main word lines (not shown) disposed in the horizontal direction across all four block sections. Each block section has one-hundred-twenty-eight sub-word decoders. A sub-word decoder (not shown) is electrically connected to a main word line and provides four sub-word lines (not shown) in the block section. This gives a total of five-hundred-and-twelve sub-word lines in a block section.
It can be seen from the bit map of FIG. 19, that any of the groups of blocks (XBLK0 to XBLK3; XBLK4 to XPLK7; XBLK8 to XBLK11; XBLK12 to XBLK15) is selected according to row address X11 and X12. Also, a block in a block group is selected according to row address X9 and X10.
One of the one-hundred-and-twenty-eight main word lines in a block (BLK0 to BLK15) is selected according to row address X2 to X8. A sub-word decoder selects one of four sub-word lines according to row address X0 and X1. In this example, the blocks are selected sequentially from block XBLK0 to block XBLK15 as the value of row addresses X9 to X12 (with X9 being the less significant address) increases.
When a block (XBLK0 to XBLK15) is selected according to row addresses (X9 to X12), a word line within the selected block can be activated according to row addresses X0 to X8. If a block (XBLK0 to XBLK15) is not selected, all word lines within the block are unselected.
For example, when X10 to X12 have a value (000), switching row address X9 from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d switches between block XBLK0 to XBLK1.
Referring now to FIG. 20, a conventional block selector is set forth in a circuit schematic diagram and given the general reference character 800.
Conventional block selector 800 is used to select a block (XBLK0 to XBLK15) in the conventional sub-array illustrated in FIG. 19. Conventional block selector 800 has block predecoders (810 and 820) and a block decoder 830. Block predecoder 810 receives and decodes row address signals X9 and X10 and provides predecode signals XP10 to XP13 to block decoder 830. Block predecoder 820 receives and decodes row address signals X11 and X12 and provides predecode signals XP20 to XP23 to block decoder 830. Row address signals X9 to X12 are provided by an address generator, such as illustrated in FIG. 10, which will be described later. Block decoder receives predecode signals (XP10 to XP13 and XP20 to XP23) and provides a block select signal to each block (XBLK0 to XBLK15).
Block decoder 830 has sixteen AND gates (8301 to 8316). Each AND gate (8301 to 8316) receives a unique combination of predecode signals (XP10 to XP13) from block predecoder 810 and predecode signals (XP20 to XP23) from block predecoder 820. Only one of the four predecode signals (XP10 to XP13) is activated and only one of the four predecode signal (XP20 to XP23) is activated. Thus, only one AND gate (8301 to 8316) has an active output and selects one of sixteen blocks (XBLK0 to XBLK15).
Referring now to FIG. 21, a block predecoder is set forth in a circuit schematic diagram. The block predecoder of FIG. 21 can be used as block predecoder (810 or 820) in the conventional block selector 800 with references to block predecoder 820 shown in parenthesis.
Block predecoder 810 has inverters (8101 to 8104), NAND gates (8105 to 8108), and inverters (8109 to 8112). Inverters (8101 and 8103) are used for inverting row address X9, and inverters (8102 and 8104) are used for inverting row address X10. NAND gates (8105 to 8108) each receive a unique combination of row address (X9 and X10) and/or inverted row addresses (X9 and X10) and provide a predecode signal (XP10 to XP13) by way of inverters (8109 to 8112) respectively.
For block predecoder 810, in accordance with the logic values of row addresses (X9 and X10) one of the predecode signals (XP10 to XP13) have a logic value of one, while the other predecode signals (XP10 to XP13) has a logic value of zero. Thus, one of the four (one-quarter) predecode signals (XP10 to XP13) is selected. Similarly for block predecoder 820, in accordance with the logic values of row addresses (X11 and X12), one of the predecode signals (XP20 to XP23) has a logic value of one, while the other predecode signals (XP20 to XP23) have a logic value of zero. Thus, one of the four (one-quarter) predecode signals (XP20 to XP23) is selected.
A conventional block selection operation will now be explained.
An address generator, such as address generator 500 illustrated in FIG. 10, receives external addresses (A0 to Aj) and latches the value of the external address in latching circuits (503-0 to 503-j) synchronously with and external clock CLK. At this time, based on the value of a row address strobe signal RASB, the latched address values are latched in row address latching circuits (504-0 to 504-j) and provide row addresses (X0 to Xj).
Row addresses, such as X13 and X14, are used to select a bank, which will be described later. Row addresses (X9 to X12) are applied to block selector 800 to select a block (BLK0 to BLK15) as described earlier. Row addresses (X0 to X8) are applied to a row decoder (not shown) and used in selecting a main word line and sub-word line as described earlier. Data bits from memory cells connected to selected sub-word lines are then latched in sense amplifiers.
After a predetermined time period (tRCD) after the row addresses (X0 to Xj) were latched, newly applied external address signals (A0 to Aj) are latched in column address latching circuits (505-0 to 505-j) as column addresses (Y0 to Yj). This is done in the same general manner as the latching of the row addresses (X0 to Xj) except the column addresses (Y0 to Yj) are latched based on the value of a column address strobe signal CASB. At this time, a sense amplifier or group of sense amplifiers may be selected, based on the column address (Y0 to Yj).
In this way, data is read or written from/to selected memory cells.
In the above conventional case, the block (BLK0 to BLK15) is selected based on row addresses X9 to X12. The row within the selected block is selected based on row addresses X0 to X8. Both the number of blocks (sixteen) and the number of rows (five-hundred-and-twelve) with a block are powers of two (2n, where n is an integer). In the conventional example mentioned above, the memory cell array is divided into two to the fourth power (sixteen) blocks (BLK0 to BLK15).
The reason for dividing the memory cell array into a plurality of blocks is to reduce the number of memory cells connected to one bit line, so that the capacitance ratio (Cd/Cs) is maintained. However, as the memory capacity is made larger, the number of blocks increase further, which can lead to an increased chip size. On the other hand, if the number of blocks is kept the same as the memory capacity is made larger, the capacitance ratio (Cd/Cs) is increased and reading errors may occur. If the capacitance ratio is set to a maximum allowable capacitance ratio (Cd/Cs), the blocks may not be divided evenly into a power of two and would complicate the decoding and may increase the time to select blocks and word lines.
In view of the above discussion, it would be desirable to provide a semiconductor memory device having a method for setting the number of blocks to a number other than a power of two. It would also be desirable to provide a method of selecting blocks when the number of blocks is a number other than a power of two. It would also be desirable to provide the above without unduly complicating the block selection and increasing selection time.
According to the present embodiments, a semiconductor memory device can include a memory cell array. The memory cell array can be divided into a number of blocks that is not a factor of two. The blocks may be arranged into repeated groups of blocks.
According to one aspect of the embodiments, each block group may include an uneven number of blocks.
According to one another aspect of the embodiments, a group of blocks may include a center block. The group of blocks may have a bit map that is symmetrical around a center of the center block.
According to another aspect of the embodiments, the semiconductor memory device may include a block selector coupled to receive addresses and select a block.
According to another aspect of the embodiments, the block selector can include a block predecoder for providing select signals for selecting a group of blocks.
According to another aspect of the embodiments, the block selector can include a block predecoder for providing select signals for selecting a block from a group of blocks.
According to another aspect of the embodiments, the plurality of blocks may be addressable by a plurality of addresses and at least one higher order address may select one of the plurality of block groups.
According to another aspect of the embodiments, a first block from the plurality of blocks may have fewer rows than a second block from the plurality of blocks.
According to another aspect of the embodiments, a first block from the plurality of blocks may include normal rows and filler rows. A second block from the plurality of blocks may include normal rows, and the number of normal rows in the second block may equal the number of normal rows plus filler rows in the first block.
According to another aspect of the embodiments, the filler rows may be redundant rows that can be used to replace a normal row.
According to another aspect of the embodiments, the block selector may include a plurality of block decoders, each block decoder may receive a block select signal from a first predecoder and a block group select signal from a second predecoder.
According to another aspect of the embodiments, an address generator may include row address latching circuits for latching row addresses and column address latching circuits for latching column addresses.
According to another aspect of the embodiments, the address generator may also include block address latching circuits for latching block addresses. Each block address latching circuit may include an exclusive OR function.
According to another aspect of the embodiments, block addresses may be supplied to a block decoder. Row addresses may be supplied to a row decoder. The block addresses may provide a symmetrical bit map. The row addresses may provide a non-symmetrical bit map.
According to another aspect of the embodiments, the semiconductor memory device may be a dynamic random access memory (DRAM) having a memory cell including a cell transistor and cell capacitor. The memory cell may be coupled to a bit line having a bit line capacitance. The number of blocks may be determined by a ratio of the capacitance of the bit line and the capacitance of the cell capacitor. The DRAM may be a synchronous DRAM (SDRAM).